This invention is directed to a process by which refractory metal contacts are made to various portions of a group III-V semiconductor substrate for electrical connection to different portions thereof. The process is particularly useful for formation of ohmic contacts of molybdenum and other refractory metals to ion implanted p-type gal ium arsenide.
Almost every semiconductor electronic substrate has the requirement for ohmic contacts to provide electrical connection to the various electronic components thereof formed in the semiconductor substrate. The pursuit of ohmic contacts has been the subject of much study. In general, for gallium arsenide the best contacts have been fabricated by an alloy techniques where a doping species, such as zinc, is coevaporated with a more noble metal, such as gold, onto the contact area. The deposition is then heat treated for a brief period to allow the zinc to heavily dope the interface layer between the gallium arsenide and the noble metal. The drawback to this process is that the heat treatment temperature must be relatively low to limit disastrous alloying- of the noble metal with the gallium arsenide. Indeed gold forms a liquid phase with gallium arsenide at relative low temperatures of about 350.degree. C. and is known to give rise to a non-uniform interface with the gallium arsenide.
This problem is also evident in gold alloys as for example the AuGe/Ni alloy discussed by U.S. Pat. No. 4,808,545 to Balasubramanyam et. al. This patent notes both the lateral migration and the vertical transport of gold causing electrical shorting of the devices.
Thus while gold and other noble metals may be useful for ohmic contact formation utilizing low temperature processing, in device fabrication which require subsequent high temperature processes such as sputter deposition or plasma etching, noble metals can not be used for ohmic contacts. Since high temperature processing is very advantageous in gallium arsenide device fabrication, the use of noble metal for ohmic contacts prior to the completion of all high temperature processes can not be practiced with gallium arsenide.
In silicon substrate technology, use of refractory metals such as molybdenum for contacts results in the formation of new molecular species. These new molecular species are silicides. If all of the refractory metal is not consumed in the formation of the silicide subsequent high temperature processes can result in further chemical reaction of both the base silicon substrate and any dopant species to form further silicide. This could deplete both the dopant species and the substrate and thus could change (in potentially uncontrolled manners) the characteristics of the device.
In gallium arsenide the alloying heat treatment to obtain zinc doping of an interface layer is at about 450.degree. C. to 500.degree. C. Use of an implanted metal ion to connect to a buried base, subsequent to the placement of an ohmic contact, requires heat treatment of the substrate to activate the metal ion implanted connector therein. When zinc is used as the implanted connector, the ion implant activation temperature is in the range of 800.degree. C. to 900.degree. C., and thus is incompatible with the temperature limitations of a previously applied gold-zinc or other noble metal ohmic contact.
Previous work has been done in attempting to apply molybdenum as a contact to p-type gallium arsenide. Those contacts generally were made to bulk doped gallium arsenide, and the lowest contact resistance which had been achieved was in the order of 4.times.10.sup.-5 ohms/cm.sup.3 on gallium arsenide doped at 1.times.10.sup.19 /cm.sup.3. Lower contact resistance is desirable.
The above reference U.S. Pat. No. 4,808,545 conducts an ion implantation to create n+type source and drain region in a FET device. After these n+type regions are formed they are alloyed with a quarternary layer of indium, germanium, molybdenum and tungsten contact metallurgy and then capped with a silicon dioxide layer for passivation prior to a high temperature anneal and dopant activation step. This ion implantation however is not used to connect a previously buried layer to surface metalization, the ion implant does not form a p-type connecting zone, consequently ohmic contacts to p-type regions are not formed and an additional photoresist lift-off stencil masking step to define the geometry of the metalization is necessary subsequent to the ion implantation.
In a further patent also for a FET device, U.S. Pat. No. 4,463,366 to Ishii et. al., while p-type regions are formed by ion implantation and connected metalization to those regions are formed, the process of this patent requires the use of an intermediate masking step for the metalization. Even with this additional masking step the resulting metalization does not form exclusive p-type region ohmic contacts but concurrently also directly contacts n-type regions adjacent to the p-type regions with resulting Schottky junctions in the metalization directly interspaced between adjacent ohmic contacts. Further, annealing must be effected prior to metalization. Additionally an etch must be effected after the anneal but prior to the metalization. Such an etch results in removal of implant ions which migrate to the substrate surface during the anneal. A direct consequence of such ion removal is the reduction of the dopant concentration of the implant zone.